18. Scan Compression Scan chain group 1 Scan chain group 2 Scan chain group N E x p a n d e r C o m p r e s s o r Scan in 1 Scan in 2 Scan in N
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21. What is the Problem? 42% Yield 77% Yield Interactions Between Design and Manufacturing Design 1 Design 2
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23. Scan based diagnostics Failure Information Failure Diagnostics Information Defect suspect coordinates Defect information Layout mapping ATPG based failure diagnostics Physical Failure Analysis Manufacture Test Wafer
As we stack more metal layers, we will find more and more metal structure related faults
Device parameters are more statistical. So, a hard limit cannot be set. Instead, it has to be learnt. Each parameter in itself might be within bounds, but taken together, it might fall in an outlier category. If we set test thresholds, we might lose too much yield or have DPM issues. So, we have to adopt methods like statistical test where we learn based on volume testing and eliminate outliers. If the part is working at a higher frequency, it does not imply that it is good. Is it operating at the best intrinsic frequency that it can. A part designed to work at 250 Mhz works at 300 MHz. Should I accept it. In SPP, I keep adapting my tests based on what I see.
“ Meeting Nanometer DPM requirements through DFT, ISQED 05 http://www.semiconductor.net/articles/images/SI/20020801/six0208def2a.jpg http://www.semiconductor.net/articles/images/SI/20020801/six0208def2a.jpg Aluminum is based on deposting a metal layer and then removing the extra material. So, we are more prone to shorts. Cu processes are based on depostion and hence are prone to opens, resistive vias, shorts
(ITRS 2001) Test costs are on the rise while cost of manufacturig the transistors are increasing. Cost of transistor testing is : more defects to be covered, more integration => more tester data volume, more advanced ATEs
P. Nigh and A. Gattiker, “Test Method Evaluation Experiments and Data,” Proceedings of the International Test Conference, 2000, pp.454-463.
The problem at a high level is quite simple. What does a designer need to do to get a design that yields properly? DRC and simulation are no longer enough. What new is required?
The problem at a high level is quite simple. What does a designer need to do to get a design that yields properly? DRC and simulation are no longer enough. What new is required?
Yield accelerates faster and reaches higher than the normal yield. This assumes that the yeild improvement rate is 3x times the original rate
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